In many data communication applications the transmission of data values involves the encoding of data values at a transmission end, and the decoding of such encoded data values and a receive end. The “weight” of a transmitted data value (i.e., the number of ones versus the number of zeros) can affect the reliability of the data signal and/or provide a way of detecting transmission errors. In particular, in the event the number of ones exceeds the number of zeros, a system will develop a running disparity that is “positive”. Conversely, if the number of zeros surpasses the number of ones, a system will develop a running disparity that is “negative”. Either case can adversely affect transmission quality.
Consequently, for many type of transmission media it is desirable to seek a running disparity as close to zero as is possible.
Because data values are commonly processed in bytes, a very common type of encoding/decoding scheme is 8-bit/10-bit (8B/10B). That is, an eight bit byte is encoded into a ten bit value for transmission. Received 10-bit encoded values are decoded back into bytes.
Currently, 8B/10B encoding/decoding is a widely used scheme for error detection in conventional data communications and processing systems. For example, an unexpected running disparity value can indicate the presence of an error. However, such encoding/decoding can have additional advantages as well. In particular, in addition to improving transmission characteristics as noted above, such encoding decoding can enable clock recovery in certain applications, and can allow for easy delineation between control and data values (symbols).
To better understand various aspects of the present invention, a conventional 8B/10B computation model is shown in FIG. 6. FIG. 6 shows an encoder 600 that can receive input data values at an input 602, and provides output data values at an output 604. Any computation to generate an output value from an input value is dependent upon a previous running disparity value provided at a running disparity output 606. In the particular example of FIG. 6, a running disparity value is passed on for a next computation operation by flip-flop 608, which couples such a value to disparity input 610.
One very particular example of a conventional encoder/decoder, such as that shown as 600 in FIG. 6 is shown in FIG. 7. An encoder 700 can include compute blocks 702-0 to 702-3, inverters 704-0 and 704-1, and multiplexers (MUXs) 706-0 and 706-1. Compute blocks 702-0 and 702-1 can receive an input data value (or portions thereof) to generate non-inverted and inverted input values for MUXs (706-0 and 706-1). In addition, compute blocks 702-0 and 702-1 can generate disparity control values for compute block 702-3. According to disparity control values, compute block 702-3 can output inverted or non-inverted values at MUXs (706-0 and 706-1) to thereby generate an output value.
It is understood that the conventional block of FIG. 7 can be implemented to provide encoding functions, or alternatively, decoding functions.
In a conventional multiple data path arrangement, such as one that provides 8B/10B encoding/decoding, a running disparity value can be sequentially passed from the computation of one input value to the next. One example of such an arrangement is shown in FIG. 8.
FIG. 8 is a block schematic diagram showing a system that includes N+1 data paths, each of which computes an output value DOUT_0 to DOUT_N from a corresponding input value DIN_0 to DIN_N. A system 800 can include compute logic (CL) blocks 802-0 to 802-N. In the above arrangement, a running disparity from a first input value DIN_0 is computed by CL block 802-0 and provided at running disparity output 804-0. Such a running disparity value is the provided as an input to CL block 802-1, corresponding to the next input value (DIN_1). The computation of the resulting output value DOUT_1 by CL block 802-1 is dependent upon such a disparity value. As understood from the figure, a running disparity value from CL block 802-1 is provided as an input to CL block 802-2, and so on. Finally, a running disparity value for a last CL block 802-N is fed back to first CL block 802-0, by way of flip-flop 806.
In this way, the computation for one input value is dependent upon a running disparity generated in the computation for a previous input value. That is, each CL block must hold off a performing a computation until a previous running disparity value has been calculated.
While the above conventional multiple path encoding system can provide a large number of encoded values in parallel, such a system can have some disadvantages. One disadvantage can be that if Td is a compute delay (i.e., an encoding or decoding delay of a compute block), a total delay in computing all encoded values can be Td*(N+1), where N+1 is the number of input values in the data path.
In light of the above, it would be desirable to arrive at some way of providing multiple data path encoding that does not suffer from the delay of conventional systems, like that described above.